DivyajyotiPat

DIVYAJYOTI PATRA

Hi I am a Student in Dharmsinh Desai University, currently Pursuing B.Tech Sem4.
I am well versed in C++ , Python, Scilab, Verilog HDL. I did participate in E-yantra 2022-23. I am very much interested in CMOS VLSI Design.

Projects

Railway Storage Security System

A PIN protected Storage at your fingertips...HTML/CSS, Quartus II, Modelsim, EDA playground, Verilog

Skills

Python
C++
Verilog